Relying on static power being significantly lower means the heat requirements for chips is easier. But that means the clock speeds are significantly slower since you can't switch as fast without melting the chip. In particular, I see challenges as MoS2 dissipates heats different than silicon. That said, we are solving this problem for stacked chips already (think 3d cache or 3d nand chips).
How would heat dissipation work with these layers semiconductors? Am I mistaken or is cooling usually the key challenge?
Relying on static power being significantly lower means the heat requirements for chips is easier. But that means the clock speeds are significantly slower since you can't switch as fast without melting the chip. In particular, I see challenges as MoS2 dissipates heats different than silicon. That said, we are solving this problem for stacked chips already (think 3d cache or 3d nand chips).