- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Oh, I didn't notice this capacitor bug, I changed it to add an enable gate for 2.4 (for context, i created 2.4 after 2.7 b/c i thought 2.7 wasn't obvious enough for some ppl). 2.4 kind of needs the enable pin b/c of how my simulation system works.
Yeah, I felt pretty conflicted on the capacitors whilst building, theres actually a note about this in the capacitor info block in later levels, but I couldn't really make a true capacitor compatible with the underlying simulation system I had built (I should have thought it through from the start).
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
Since we're in feedback mode, 2.16 has no BitLineBar reference to feed to the comparators. I had to cheese the level by connecting the "capacitor" outputs straight to the outputs, and it worked.
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
Agreed, truth tables one is important. But it's backwards, you test people on truth tables before teaching them.
If someone is seeing this for the first time they may have never seen some of those gates and you quiz them.
Then finally after passing the quiz, you define NAND and NOR and Inverter.
Swap the teaching one to be the intro to the truth tables one.
Second bit of feedback is the timer. Increase the time allotted. I know them very well and still was struggling to get all the input correct before the timer hit. Or consider possibly just eliminating the timer completely - if your goal is to be sure that they know them.
good point, made an update that added difficulty levels to the minigames (handles the timer), and i'll probably move the truth tables minigame to after the user builds the truth tables, thx
Anyone who likes this should also take a look at: https://store.steampowered.com/app/1444480/Turing_Complete/
At the end you have your own CPU with your own assembly language.
Sadly stuck in early access since forever with some very rough edges
They're bikeshedding pretty hard, making their own language for the simulation. You can access the unstable branch through steam, it was getting fairly regular updates last I checked.
Steam discussions seem to imply there is still something happening https://steamcommunity.com/app/1444480/discussions/0/7674379... But communication is definitely subpar. I completed it a few years ago, was fun but having prior knowledge about digital circuits is a must have in my opinion.
I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level.
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
lol, mb. As in understand it, its that the colors of the bg make it seem like its wires when its not, I'll change the color theme a bit to fix (plz correct me if my understanding is wrong)
Yes, that's the issue: the (thick) solid grey "major axis" lines on the background seemed to be a wire.
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
the part that tripped me up is 0 showing in deep RED and I thought that meant I was doing something wrong. I came here, read this and realized I was actually right and then pressed the Run tests button and passed. This is a UX thing you'd want to address
This looks really cool, although I personally seem to lack the absolute basic knowledge that is required to make sense of the tutorial messages, so I couldn't even figure out the first level.
Thanks for telling me this, I actually made an act 0 that went through the basics + physics of the pmos and nmos transistors, but i scrapped it b/c i couldn't get it to look like I wanted it to, will add it back
Glad I'm not the only one! I love these kinds of games; played the heck out of Turing Complete and Zachtronics' Engineer of the People... But I'd never heard of 3 state logic until today.
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
I would have really liked to have a temporary node to test the outputs.
Better than that, I would have liked to see the truth table update in real time without running the tests.
You need to have a, "Okay, I've tried 10 times, it's not working, what's the answer?" button. That will help not just us rubes who can't understand, but also in the off chance something is broken and even "correct" answers are being rejected.
makes sense, adding to the next push (in the interim, u can also use the copy circuit button to ask gpt if ur correct or not), also, what level is this? (if u dont mind me asking)
Oh that's what the "copy circuit" button does. I have been trying to paste circuits from previous levels into subsequent ones and wondering what I was doing wrong
Nw! This is an excellent game overall. I have always had a REALLY hard time understanding the electronics behind gates and this has been super helpful. I understood the physics behind NMOS and PMOS, and separately what logic tables represented and could be combines for higher order execution. The first few levels, constructing NANDs and NORs, has always been a puzzle - until today! Thank you <3
as a learning resource, it would be great it acronyms were expanded at least once. nmos, pmos, gnd, vdd all in the first 5 seconds or so, and i didnt see anywhere that actually said what those stood for
otherwise, looks polished and fills in a nice niche!
There's the info boxes that it could be added to, that way it is always available at a mouse click.
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
I had an arc 0 where it went through some of these topics more in depth and explained them, deleted it b/c i couldn't get the UI to look right. I've pushed a bandaid that should fix this, but ill bring in arc 0 (it seems this is a popular request) after polishing it (ill also make it optional)
This is super cool but part of me wishes I could skip to the later levels rather than redo college homework from a decade ago. Maybe that ruins the fun but also slogging through the early levels (especially when the UI is a bit rough around the edges and doesn't support copy paste) isn't fun either.
Any easy way to make this usable on mobile? In portrait mode things are unreadable, zoom and scrolling do not work. Landscape is even worse as everything is out of view (and zoom/scroll do not work).
I'm confused about a difference in the NMOS and PMOS. The scenario I'm confused about is when the source is VDD and the drain is connected to GND and output.
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
Oh, the drain should only be connected to the output, not drain aswell (irl this would kill one's chip, I'll add a feature to show short-circuiting). on pmos the source should be vdd, on nmos the source should be gnd (this doesn't apply for some later levels, but does for earlier ones).
Ok you have put a lot of work in this and it looks impressive. But it needs a serious balance change. It is far too hard. Currently this may work as a brain teaser for people in the industry or people with computer engineering degrees, but it wont bring any fresh young minds into the industry. The fresh young minds will be scared off.
Teaching is challenging stuff. You have to step out of your current mindset and think with the mind of someone that sees this stuff for the first time. It is not easy to make things look easy and simple. Specifically, I think you need a lot more exploration about cmos logic, about how one side pulls the output up or the other side pulls the output down but they are never on at the same time, about how they effectively amplify the result so the output does not have to depend on the power of the input, etc. Perhaps you can try to have people design things in NMOS logic than in PMOS logic and then combine the two to make a CMOS design to see how they complement each other.
But I do not want to discourage you. This is a very promising start and you should continue if you have the time.
Also, the timed answers -- are you kidding me? The time is waaay too short. And you fail all if you fail a single answer. Oh what is 0xDE in decimal, all I have to do is multiply 16 by 13 and add 14 to that. In my head in 12 seconds. Also the time is not sufficient for filling out truth tables, especially with a laptop trackpad. I was able to pass the truth tables, but gave up on hexracing.
Ok and here are some more specific issues.
-The wires seem to snap in position in a way that they superimpose each other so it becomes very difficult to see what your circuit is doing.
- truth tables seem to be bugged. If you have more inputs than the gate whose truth table you are looking at, sometimes it will generate a fictitious truth table with extra inputs. Thus, some times i get a NOT truth table that has two inputs.
- the ground element should have its connection circle on the top, not the bottom. I realized that you can rotate by pressing R, but the site does not mention that anywhere.
Nice vibe coded project. There are a few UX holes i've encountered so far: No way to re-invoke the intro modals in each lesson after dismissal? No way to go to the next lesson if we dismiss the modal (have to go back to the tree and then click the next lesson)
Layout appears unusable on my phone on Firefox Android (both portrait and landscape). Necessary elements seem to get hidden behind others. Not sure if I'm even supposed to be able to play it without kB&m though lol :)
This would be such a good game for introducing students to digital technology! This is so fun! We just had to draw them by hand back in the dark ages of the 2010s.
100% agree - the way that you have the very subtle arrows on the transistor drains that show the actual current flow is really smart too. I struggled with visualizing the current flow in undergrad for an embarrassingly long time.
The truth tables are way too hard for me. I need time to think and the 10 seconds is way too fast. If this is intended to be a teaching resource, avoid timers IMHO. It needlessly excludes people.
makes sense, idk if i want to remove times altogether (i personally found it fun + i want the game to be fun for all levels of familiarity), but ill add a modal to explicitly select difficulty level at the start of the racer game, i def agree w/ u overall
The 2.13 level ("hex racer") is kind of pain. Apparently I'm not fast enough at dividing/multiplying by 16... when I get something like "convert 0xB3 to decimal"
if you solve a level, then press "next level", then solve that next level - then it still shows the original level (I think it just gets hidden below the new one and then reappears after a solve?)
first level is impossible to solve for me! Hint or showing solution did not work! Also adding multiple sources or ground behave differently than connecting to the same.
Next update has warnings about bus contention (multiple things into one node) when its an issue, and will have a proper show solution button.
For level 1.1 the solution is basically to take the ground and use that as a singular input to the source pin of an nmos transistor, let the input to the level be the gate pin of that same nmos transistor, and to let the drain (top) pin of that nmos transistor connect to the level's output
A nice game, though the truth table lighting round is pretty punishing! Big contrast to the circuit building part where you can take your time. Personally I'd drop the time requirements from that quiz section.
lol, I hadn't seen that video before but its a good one. Na, this is the guide to comp arch that will (hopefully) end all instances of toil over documentation for any sort of processor when learning
yeah, I felt that when playing myself, do u think this level is not necessary given previous levels? (it would also help me if u indicated ur level of familiarity w/ the concepts s.t i can calibrate)
It's always nice to see educational games like that.
A lot of new learners (like me) are just looking at the high level stuff, where the computer "just works"...
I've made it through about the first ten parts of section 2. Some additional feedback I've put together:
* Sometimes explanations are overly lacking, other times they get repetitive. This feels like it needs to be accompanied by a course to fully deliver value. For instance, we're kind of thrown into truth gates without having really gone over them. And understanding how to combine NMOS and PMOS gates could use a better intro. Once I knew the answers, I got my brain to reset to my VLSI course from college, but I think a better primer could've accomplished that. In other places, I feel like we get more refreshers on some components than others.
* The routing algorithm needs to be better. I get a lot of staircase wires and straight up overlaps.
* Right clicking should clear attempted connections.
* There should be away to delete components you've placed. Maybe I just couldn't figure it out.
* I think icons should be included on the components pane. I kept clicking NOR when I wanted NOT and a better visual cue would have helped.
* It feels like difficulty is all over the place. Perhaps this is corrected with better explanations, but creating the NAND gates and NOR gates were much more difficult compared to AND and OR. Perhaps actually having us construct those gates without NOT would change the difficulty curve.
* The success overlay shows up too fast. Especially on levels that are just a demonstration (like the NMOS and PMOS Again levels) you don't get to to see everything the level is trying to demonstrate before the level announces that you have succeeded.
* In the intros, when there are new components, their description pops in. Instead, it should just advance like a slide. It's very jarring.
* Also, it's unclear that those aren't part of the intro. Maybe instead of popping them up, flash the little information icon next to them.
* What you call a capacitor I believe is actually a combination of a transistor and a capacitor. I think people will be hard pressed to find documentation on a capacitor with an enable switch. But, then you use this same capacitor to form a 1T1C cell. I'm rather confused.
* Many times when I finished a level, the circuit would switch to a prior level's solution.
* Some components have the same letters for every terminal (e.g. half-adders), meaning you need to scroll over the terminals to know what they do.
* Some levels have many test cases, and there's now way to see them all.
* Level 2.3 talks about us having registers, but we never covered those. In fact, I think we're still a ways away since we need to get from switches to flip-flops then to registers.
There isn't much order to this. Just what I recorded while working through it. Overall it's pretty good, I just think polish would got quite a ways.
Thank you for sharing this! I'm really excited to get to the more GPU specific parts. I basically did this for CPUs in college and I'm excited to see what preconception and missing conceptions I have for GPUs.
Thanks for all the feedback! I've fixed some of these issues (e.g., capacitor levels, switching back to prior levels upon finishing / refreshing, deletion (theres a sign when you hover a component now)), but many of them i'll be fixing today.
I'll be uploading arcs 3 and 4 soon (which will be programming the CPU and the start of GPU arch soon (people have gone through arcs 1 and 2 slightly faster than I expected)
The aspect that I especially like is covering the 3-state aspect of the logic. Studying CS, it was kind of vaguely mentioned, and we skipped over to doing logic diagrams with gates and the assumption of 2-state logic really quickly...and it seems like most games do that kind of skip too. Working at the transistor level grounds it better to the actual components.
So, is there anything about GPU's in here right now?
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
Not at the moment unfortunately, I've actually completed a good chunk of the GPU levels, but I think ppl will need to do act 2 and 3 for it to make sense
Love it, thanks! Would you mind making it possible for me to see my "circuit" after running the tests? Currently, I can't go back to the circuit I created.
I haven't pushed to github (Will do this soon), but I believe that i've fixed the issue (also, by wanna fix this bug I meant I want to fix this bug, (but would def also appreciate help if ur interested, the mechanics of this game ended up being a bit more complex than I initially envisioned lol))
No problem. I am currently on the third level I think and my laptop fan ramps up, so I closed the tab and it stopped. Also, how can I delete e.g. transistors again?
I see, I'll try to reduce the load, i'm using canvas 2d so that could be causing it. you can delete by selecting then pressing the delete button (will also allow right click to delete in the next push, since i do this for wires)
Yeah, nand game was part of the inspiration, I felt that it was good but was a bit plain UI/UX wise and obfuscated / simplified some things that it shouldn't have
oh its b/c of the contention between the outputs of the ands for the answer, u need an or gate to merge them (ill add an update w/ visual feedback for these sorts of thigns)
We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.
Yeah, I had added it to make it compatible w/ my simulation system, just changed how I was handling the levels altogether, if it still has 3 try doing a hard refresh (Ctrl + Shift + R on windows, cmd + shift + R on macos)
This is great!
Some comments:
- I didn't like the "truth tables" one, I got many duplicate questions and for some reason I got only one second for the first question. The rest of the questions I managed to answer correctly but I still got only one start out of three?
- I got very confused by the capacitor. Capacitors do not have an "enable" gate! In fact, in 2.7 (1T1C) you are supposed to build the enable gate -- with a transistor. So currently, you can just simply not build the enable gate and use the one already in the primitive, meaning you don't need the NMOS gate at all.
Was this made using LLM-assistence? (Not judging, I'm just interested!) I'd love to hear more about your workflow and how you managed to produce a good UI as it's something I couldn't do if my life depended on it, and it's a skill I'd like to learn.
Oh, I didn't notice this capacitor bug, I changed it to add an enable gate for 2.4 (for context, i created 2.4 after 2.7 b/c i thought 2.7 wasn't obvious enough for some ppl). 2.4 kind of needs the enable pin b/c of how my simulation system works. Yeah, I felt pretty conflicted on the capacitors whilst building, theres actually a note about this in the capacitor info block in later levels, but I couldn't really make a true capacitor compatible with the underlying simulation system I had built (I should have thought it through from the start).
Ill fix the truth tables bug (i think i know the issue), the stars come from playing in endless mode
I used claude quite a bit, it struggled through a lot of this (wiring and simulation systems in particular), but managed to crank this out, for the graphics i was extremely detailed in terms of what i wanted i'd say
Since we're in feedback mode, 2.16 has no BitLineBar reference to feed to the comparators. I had to cheese the level by connecting the "capacitor" outputs straight to the outputs, and it worked.
On the capacitor though, the capacitor level is weird as you don't build the capacitor charge system with transistors. Though I definitely get that the simulation engine is for digital stuff, not analog :)
Also a general feedback on the time-based challenges: dial them back. A lot. Most of them are just not interesting and have zero learning value. In fact, the "DRAM refresh" one just made me quit the game (clicking on 8 rows to keep them fresh). Okay, 10s is enough, I got the point. No need to hold up for a whole minute. Kinda same for the hex one. However, some of them are good, and the UI for the binary ones is great, especially for the two's complement one!
Small nitpick on the UI: some blocks don't have their connections aligned with the grid, making the wiring OCD-incompatible. But that's minor. It's a shame since the wire routing algorithm works quite well overall, and I'm impressed an LLM could produce that good of an UI!
Otherwise, quite a fun little game, if slow paced when one already knows some bits of digital logic. Keep up!
lol, I encountered the same thing w/ the Dram one in particular during testing (I passed it by using number keys, but probably was a sign to remove)
Thanks, I appreciate all the feedback, fixes coming in the next push
Agreed, truth tables one is important. But it's backwards, you test people on truth tables before teaching them.
If someone is seeing this for the first time they may have never seen some of those gates and you quiz them.
Then finally after passing the quiz, you define NAND and NOR and Inverter.
Swap the teaching one to be the intro to the truth tables one.
Second bit of feedback is the timer. Increase the time allotted. I know them very well and still was struggling to get all the input correct before the timer hit. Or consider possibly just eliminating the timer completely - if your goal is to be sure that they know them.
good point, made an update that added difficulty levels to the minigames (handles the timer), and i'll probably move the truth tables minigame to after the user builds the truth tables, thx
Anyone who likes this should also take a look at: https://store.steampowered.com/app/1444480/Turing_Complete/ At the end you have your own CPU with your own assembly language. Sadly stuck in early access since forever with some very rough edges
Love this game. Does anyone know if developers are still active?
They're bikeshedding pretty hard, making their own language for the simulation. You can access the unstable branch through steam, it was getting fairly regular updates last I checked.
Steam discussions seem to imply there is still something happening https://steamcommunity.com/app/1444480/discussions/0/7674379... But communication is definitely subpar. I completed it a few years ago, was fun but having prior knowledge about digital circuits is a must have in my opinion.
wow - will try it today!
I worked on deep sub-micron, full custom mixed-signal integrated circuits for more than a decade, and I can't pass the first level.
> Wire an NMOS transistor so that when In is 1, the output is pulled to ground (0). When In is 0, the output should be unconnected (Z).
Certainly:
(a) The nMOS has 3 connections: its drain is only connected to the output (no +Vdd supply), it's source is tied to ground, it's gate is tied to the signal input
(b) When the gate (input) is driven high, the nMOS transistor turns "on," connecting the output to the source (which is grounded). This acts as a "pull-down network"
(c) When the gate is driven low, the nMOS turns "off," leaving no connection to the output. This is equivalent to a "high-impedance" / "unconnected" / "Z" output
Fails 1/2 tests
(Edit) - I thought the light grey, thick line on the background grid was a wire from "input" to the transistor's gate. It is not. You need to explicitly add a wire from "input" to gate :\
I'm a total doofus with no relevant experience and neither could I.
Adding intro levels today!
lol, mb. As in understand it, its that the colors of the bg make it seem like its wires when its not, I'll change the color theme a bit to fix (plz correct me if my understanding is wrong)
Yes, that's the issue: the (thick) solid grey "major axis" lines on the background seemed to be a wire.
If I could make a recommendation, get rid of the grid lines entirely and only have 'dots' at regular spacing. Here's what Cadence Virtuoso looks like (the most popular circuit schematic tool for integrated circuit design):
https://www.eecs.umich.edu/courses/eecs311/f09/tutorials/cad...
Will do, thx! Coming in the next push
consider a colorblind mode that uses patterns instead of colors for those of us that are color-challenged
the part that tripped me up is 0 showing in deep RED and I thought that meant I was doing something wrong. I came here, read this and realized I was actually right and then pressed the Run tests button and passed. This is a UX thing you'd want to address
Did you switch to software?
This looks really cool, although I personally seem to lack the absolute basic knowledge that is required to make sense of the tutorial messages, so I couldn't even figure out the first level.
Thanks for telling me this, I actually made an act 0 that went through the basics + physics of the pmos and nmos transistors, but i scrapped it b/c i couldn't get it to look like I wanted it to, will add it back
Glad I'm not the only one! I love these kinds of games; played the heck out of Turing Complete and Zachtronics' Engineer of the People... But I'd never heard of 3 state logic until today.
Really threw me for a loop! I'm still trying to wrap my head around making level 3's NOT gate.
This is such a cool idea, definitely the first 3-state circuit puzzler I've seen! Throw a cute story over it and I bet this would get some takers on Steam.
Neat idea!
Ive added this to the HN Arcade! https://hnarcade.com/games/games/mvidia
Thank!
I would have really liked to have a temporary node to test the outputs. Better than that, I would have liked to see the truth table update in real time without running the tests.
You need to have a, "Okay, I've tried 10 times, it's not working, what's the answer?" button. That will help not just us rubes who can't understand, but also in the off chance something is broken and even "correct" answers are being rejected.
makes sense, adding to the next push (in the interim, u can also use the copy circuit button to ask gpt if ur correct or not), also, what level is this? (if u dont mind me asking)
Oh that's what the "copy circuit" button does. I have been trying to paste circuits from previous levels into subsequent ones and wondering what I was doing wrong
lol, mb; ill make that more clear (ill also give the ability to copy things cross level and intra-level)
Nw! This is an excellent game overall. I have always had a REALLY hard time understanding the electronics behind gates and this has been super helpful. I understood the physics behind NMOS and PMOS, and separately what logic tables represented and could be combines for higher order execution. The first few levels, constructing NANDs and NORs, has always been a puzzle - until today! Thank you <3
It sounds great, it remembers to me:
- https://www.nand2tetris.org/
- https://nandgame.com/
as a learning resource, it would be great it acronyms were expanded at least once. nmos, pmos, gnd, vdd all in the first 5 seconds or so, and i didnt see anywhere that actually said what those stood for
otherwise, looks polished and fills in a nice niche!
There's the info boxes that it could be added to, that way it is always available at a mouse click.
That said, I'm not sure how useful expanding most of the acronyms would be. Names like Negative/Positive Metal Oxide Semiconductor aren't exactly self-explanatory, Vdd isn't really an acronym, etc..
I had an arc 0 where it went through some of these topics more in depth and explained them, deleted it b/c i couldn't get the UI to look right. I've pushed a bandaid that should fix this, but ill bring in arc 0 (it seems this is a popular request) after polishing it (ill also make it optional)
Great game! For learning, might be nice to see some commentary or example (model) solutions after beating a level.
Yeah, I've actually been planning to add this in, might have gemini look at your circuit config and give its opinion, alongside dynamic hints
I have been looking for something like this for so longggg! THANK YOU
This is super cool but part of me wishes I could skip to the later levels rather than redo college homework from a decade ago. Maybe that ruins the fun but also slogging through the early levels (especially when the UI is a bit rough around the edges and doesn't support copy paste) isn't fun either.
That was great fun, an interactive refresher on my EE studies. Thank you so much for creating it.
If anybody can create something similarly interactive, educational and hands-on for microbiology or robotics, I am happy to sponsor your cost.
Huge fan of this! I love learning-by-doing and this captures that cycle perfectly.
Any easy way to make this usable on mobile? In portrait mode things are unreadable, zoom and scrolling do not work. Landscape is even worse as everything is out of view (and zoom/scroll do not work).
Yeah, i'm planning to make it mobile compatible in the coming day(s), i didn't plan for this to be mobile originally, so it kind of sucks on phone
I'm confused about a difference in the NMOS and PMOS. The scenario I'm confused about is when the source is VDD and the drain is connected to GND and output.
For the PMOS, the output toggles between 1 and 0 (opposite the gate) as expected. However, for the NMOS, the output is always 0.
I don't understand why GND pulls VDD down to 0 for the NMOS, but not the PMOS.
Oh, the drain should only be connected to the output, not drain aswell (irl this would kill one's chip, I'll add a feature to show short-circuiting). on pmos the source should be vdd, on nmos the source should be gnd (this doesn't apply for some later levels, but does for earlier ones).
Ok you have put a lot of work in this and it looks impressive. But it needs a serious balance change. It is far too hard. Currently this may work as a brain teaser for people in the industry or people with computer engineering degrees, but it wont bring any fresh young minds into the industry. The fresh young minds will be scared off.
Teaching is challenging stuff. You have to step out of your current mindset and think with the mind of someone that sees this stuff for the first time. It is not easy to make things look easy and simple. Specifically, I think you need a lot more exploration about cmos logic, about how one side pulls the output up or the other side pulls the output down but they are never on at the same time, about how they effectively amplify the result so the output does not have to depend on the power of the input, etc. Perhaps you can try to have people design things in NMOS logic than in PMOS logic and then combine the two to make a CMOS design to see how they complement each other.
But I do not want to discourage you. This is a very promising start and you should continue if you have the time.
Also, the timed answers -- are you kidding me? The time is waaay too short. And you fail all if you fail a single answer. Oh what is 0xDE in decimal, all I have to do is multiply 16 by 13 and add 14 to that. In my head in 12 seconds. Also the time is not sufficient for filling out truth tables, especially with a laptop trackpad. I was able to pass the truth tables, but gave up on hexracing.
Ok and here are some more specific issues.
-The wires seem to snap in position in a way that they superimpose each other so it becomes very difficult to see what your circuit is doing.
- truth tables seem to be bugged. If you have more inputs than the gate whose truth table you are looking at, sometimes it will generate a fictitious truth table with extra inputs. Thus, some times i get a NOT truth table that has two inputs.
- the ground element should have its connection circle on the top, not the bottom. I realized that you can rotate by pressing R, but the site does not mention that anywhere.
Nice vibe coded project. There are a few UX holes i've encountered so far: No way to re-invoke the intro modals in each lesson after dismissal? No way to go to the next lesson if we dismiss the modal (have to go back to the tree and then click the next lesson)
Hi everyone, commenting to address feedback:
- Made timed minigames optional (e.g. binary tables)
- Added 7 (optional) intro levels to walk through pmos and nmos transistors
- Fixed the bug in the capacitor levels
- Changed editor bg to use dots instead of lines to fix wire confusion
Layout appears unusable on my phone on Firefox Android (both portrait and landscape). Necessary elements seem to get hidden behind others. Not sure if I'm even supposed to be able to play it without kB&m though lol :)
Yeah, its not mobile-ready atm, ill push an update to make it mobile-friendly in the next day or so
This would be such a good game for introducing students to digital technology! This is so fun! We just had to draw them by hand back in the dark ages of the 2010s.
Thx, way better (imo) than just reading slides or (god forbid) pure text describing comp arch
100% agree - the way that you have the very subtle arrows on the transistor drains that show the actual current flow is really smart too. I struggled with visualizing the current flow in undergrad for an embarrassingly long time.
The truth tables are way too hard for me. I need time to think and the 10 seconds is way too fast. If this is intended to be a teaching resource, avoid timers IMHO. It needlessly excludes people.
makes sense, idk if i want to remove times altogether (i personally found it fun + i want the game to be fun for all levels of familiarity), but ill add a modal to explicitly select difficulty level at the start of the racer game, i def agree w/ u overall
please just let me skip it. why am i doing homework in the middle of a game?
The 2.13 level ("hex racer") is kind of pain. Apparently I'm not fast enough at dividing/multiplying by 16... when I get something like "convert 0xB3 to decimal"
Time to get on zetamac (all jokes aside, it should be optional, i'll also make racer games slower + adaptive soon (today))
if you solve a level, then press "next level", then solve that next level - then it still shows the original level (I think it just gets hidden below the new one and then reappears after a solve?)
just pushed a fix
first level is impossible to solve for me! Hint or showing solution did not work! Also adding multiple sources or ground behave differently than connecting to the same.
Next update has warnings about bus contention (multiple things into one node) when its an issue, and will have a proper show solution button.
For level 1.1 the solution is basically to take the ground and use that as a singular input to the source pin of an nmos transistor, let the input to the level be the gate pin of that same nmos transistor, and to let the drain (top) pin of that nmos transistor connect to the level's output
A nice game, though the truth table lighting round is pretty punishing! Big contrast to the circuit building part where you can take your time. Personally I'd drop the time requirements from that quiz section.
Yeah, a lot of people have said similar things, I'm going to make them all optional (coming in 30 min or so)
Is this a sequel to "How to make a CPU"? https://www.youtube.com/watch?v=vuvckBQ1bME
lol, I hadn't seen that video before but its a good one. Na, this is the guide to comp arch that will (hopefully) end all instances of toil over documentation for any sort of processor when learning
This is awesome! The truth table lightning round took me by surprise, I am rustier than I thought...
One note: It isn't immediately obvious that the In/Out nodes can be connected to multiple wires, made the first few rounds harder to work thru.
I see, thx, ill add a note in the game to make it more clear
truth tables round is optional now!
love it, some level (full adder with 8 inputs) where a bit repetative, but it is fun.
yeah, I felt that when playing myself, do u think this level is not necessary given previous levels? (it would also help me if u indicated ur level of familiarity w/ the concepts s.t i can calibrate)
It's always nice to see educational games like that. A lot of new learners (like me) are just looking at the high level stuff, where the computer "just works"...
Well done and keep it up :)
Must be missing something - is there a way to save progress?
progress is saved automatically, what issue are you encountering?
The “next level” button takes you to the next level even if you haven’t solved that level’s prerequisites.
Thanks for telling me, just pushed a fix
The continue buttons in intro break for me all the time on Firefox. I can't actually finish most of them.
fixed!
I've made it through about the first ten parts of section 2. Some additional feedback I've put together:
* Sometimes explanations are overly lacking, other times they get repetitive. This feels like it needs to be accompanied by a course to fully deliver value. For instance, we're kind of thrown into truth gates without having really gone over them. And understanding how to combine NMOS and PMOS gates could use a better intro. Once I knew the answers, I got my brain to reset to my VLSI course from college, but I think a better primer could've accomplished that. In other places, I feel like we get more refreshers on some components than others.
* The routing algorithm needs to be better. I get a lot of staircase wires and straight up overlaps.
* Right clicking should clear attempted connections.
* There should be away to delete components you've placed. Maybe I just couldn't figure it out.
* I think icons should be included on the components pane. I kept clicking NOR when I wanted NOT and a better visual cue would have helped.
* It feels like difficulty is all over the place. Perhaps this is corrected with better explanations, but creating the NAND gates and NOR gates were much more difficult compared to AND and OR. Perhaps actually having us construct those gates without NOT would change the difficulty curve.
* The success overlay shows up too fast. Especially on levels that are just a demonstration (like the NMOS and PMOS Again levels) you don't get to to see everything the level is trying to demonstrate before the level announces that you have succeeded.
* In the intros, when there are new components, their description pops in. Instead, it should just advance like a slide. It's very jarring.
* Also, it's unclear that those aren't part of the intro. Maybe instead of popping them up, flash the little information icon next to them.
* What you call a capacitor I believe is actually a combination of a transistor and a capacitor. I think people will be hard pressed to find documentation on a capacitor with an enable switch. But, then you use this same capacitor to form a 1T1C cell. I'm rather confused.
* Many times when I finished a level, the circuit would switch to a prior level's solution.
* Some components have the same letters for every terminal (e.g. half-adders), meaning you need to scroll over the terminals to know what they do.
* Some levels have many test cases, and there's now way to see them all.
* Level 2.3 talks about us having registers, but we never covered those. In fact, I think we're still a ways away since we need to get from switches to flip-flops then to registers.
There isn't much order to this. Just what I recorded while working through it. Overall it's pretty good, I just think polish would got quite a ways.
Thank you for sharing this! I'm really excited to get to the more GPU specific parts. I basically did this for CPUs in college and I'm excited to see what preconception and missing conceptions I have for GPUs.
Thanks for all the feedback! I've fixed some of these issues (e.g., capacitor levels, switching back to prior levels upon finishing / refreshing, deletion (theres a sign when you hover a component now)), but many of them i'll be fixing today.
I'll be uploading arcs 3 and 4 soon (which will be programming the CPU and the start of GPU arch soon (people have gone through arcs 1 and 2 slightly faster than I expected)
Awesome project! Reminds me of Turing Complete on Steam.
Yeah, that was the inspiration, felt that it didn't go in depth enough + didn't cover other processors, so I wanted to fill that hole + make it free
The aspect that I especially like is covering the 3-state aspect of the logic. Studying CS, it was kind of vaguely mentioned, and we skipped over to doing logic diagrams with gates and the assumption of 2-state logic really quickly...and it seems like most games do that kind of skip too. Working at the transistor level grounds it better to the actual components.
Fun. 2.2 loads a blank screen for me, all previous levels were fine and 2.3 loads. Windows, Firefox 149.
Edit: Confirmed fixed.
Fixed! If you go to the level and refresh (might need to hard refresh: Ctrl + Shift + R) it should load properly now
So, is there anything about GPU's in here right now?
I didn't actually finish Act 2, but it seems to end in a conventional processor with the GPU first coming after another two acts currently under construction.
Not at the moment unfortunately, I've actually completed a good chunk of the GPU levels, but I think ppl will need to do act 2 and 3 for it to make sense
Great project! I somehow missed whole cpu architecture topic, so gonna catch up on that now
Yeah, fortunately I made cpu arch part of the game, so it'll serve great for that as well
Soooo cool! I will keep try this
I like the concept! What tools did you use to build it?
stack was mainly vite (react) + typescript pretty much (canvas 2d for the visuals)
Love it, thanks! Would you mind making it possible for me to see my "circuit" after running the tests? Currently, I can't go back to the circuit I created.
Sure, you should be able to rn though, is this after completing the level (wanna fix this bug)?
Sure, but I can't seem to find the git?
I haven't pushed to github (Will do this soon), but I believe that i've fixed the issue (also, by wanna fix this bug I meant I want to fix this bug, (but would def also appreciate help if ur interested, the mechanics of this game ended up being a bit more complex than I initially envisioned lol))
No problem. I am currently on the third level I think and my laptop fan ramps up, so I closed the tab and it stopped. Also, how can I delete e.g. transistors again?
I see, I'll try to reduce the load, i'm using canvas 2d so that could be causing it. you can delete by selecting then pressing the delete button (will also allow right click to delete in the next push, since i do this for wires)
Fixed!
truth table minigame is lmost unplayable in dark mode
also it kept showing the same table to me like 4 times
I just pushed a fix for this, so it should be better now, its also optional now
really fun :) thanks!
Cool concept, but it should be mobile friendly
Good point (I didn't really consider this), might be a bit difficult tho tbh, but i'll push this soon
Reminds me of http://nandgame.com and https://nand2tetris.org
Yeah, nand game was part of the inspiration, I felt that it was good but was a bit plain UI/UX wise and obfuscated / simplified some things that it shouldn't have
level 1.10 I put 2 AND gates and only one of them works...
I want to fix this, could you elaborate a bit (would help even more if you pressed the copy circuit and pasted the result here)
Add 2 AND gates, 1 NOT gate
G0 = D0 AND SEL
G1 = NOT SEL
G2 = D1 AND G1
G0 -> Ans
G2 -> Ans
oh its b/c of the contention between the outputs of the ands for the answer, u need an or gate to merge them (ill add an update w/ visual feedback for these sorts of thigns)
It's likely you are pulling one to ground somehow. That was a common bug I faced.
În a few years it will be the only way to explain the kids what a GPU is. Unless you work for an “AI” shop and sneak them into the data center.
Exactly :(
This is very cool!
We need more games like this so that the younger population get some sort of exposure to the hardware side of things, before AI takes over that field. I would also think that take-home electronic and soldering kits for adults and younger folks would be another way to reduce dependance on AI.
how do I remove/delete elements?
click and press delete, realizing this wasn't obvious, a fix to add a similar delete mechanism to how wires are deleted is coming
> press delete
I don't see any button labeled that
oh, as in delete on the keyboard. it shoudl also work just to right click now (might need to refresh)
...why capacitor has 3 pins ?
Yeah, I had added it to make it compatible w/ my simulation system, just changed how I was handling the levels altogether, if it still has 3 try doing a hard refresh (Ctrl + Shift + R on windows, cmd + shift + R on macos)
wow looks really cool, although seems kinda useless at first look.
damn :(
not playing past the truth tables bs
optional now!
lol (plz come back), will be optional in 30 min (lemme push)