2 points | by hn_submit an hour ago
2 comments
Intel wants to produce DRAMs again now that AI is set to permanently alter the demand for RAM. But they want to integrate DRAM with the CPU, which could lead to huge speed increases, just like Apple has done with its M-CPUs.
So uh, isn't it just L4 cache like 3D V-Cache or in Intel's own terminology, bLLC? I just don't see how they violated data hierarchy to be more useful
Intel wants to produce DRAMs again now that AI is set to permanently alter the demand for RAM. But they want to integrate DRAM with the CPU, which could lead to huge speed increases, just like Apple has done with its M-CPUs.
So uh, isn't it just L4 cache like 3D V-Cache or in Intel's own terminology, bLLC? I just don't see how they violated data hierarchy to be more useful