Core memory is very resistant to radiation. When the Shuttle computers were upgraded to semiconductor memory, radiation became an issue. The solution was to add six extra bits of storage to each word and use ECC. A background process scanned for errors and corrected them. The computer could encounter 100 bit flips per flight, so radiation was significant. (There was even an incident where a single cosmic ray flipped 14 bits.) The other problem with semiconductor memory was its volatility, so the computer had NiCd batteries for backup power to the RAM.
On the topic of ferromagnetic computing, was there ever any serious investigation of Parametron type machines for at least parts of the flight control or other critical systems where interruptions would have been very serious?
I assume you're interested in magnetic core logic computers in general, not specifically Parametrons. In the late 1950s, NASA considered core-transistor logic for a spacecraft navigation computer due to its lower power consumption. The prototype version of the Apollo Guidance Computer (1962) used core-transistor logic. But improvements in transistors made core-transistor logic less appealing, not to mention the arrival of ICs. At the end of 1962, NASA decided to use ICs for the Apollo Guidance Computer and abandoned core-transistor logic. The updated AGC kept the core memory and core rope ROM of the earlier AGC, though.
Yes, those engineering discussions must have been interesting. By that point people had a fair amount of experience in Earth orbit but between the relative newness of space and the relative newness of computers there must have been significant new engineering. Maybe the ICBM programs had some lessons.
Please write an article about that French computer
Project idea: find 64kb kb of such memory and connect it somehow into Apple2, atari and other 8bit cpus hehe
It must be possible to have some hardware adapter to map RAM into that type of memory.
Or even over serial...
ps. Related story: around 10 years ago Texas Instruments started to use FRAM in some of their 16 bit MCUs (msp430 family)
It works exactly like core memory - data still intact after power resets.
The architecture without inhibit lines is interesting. Did this make the memory faster, or was the main goal simply to reduce the number of sense amplifiers and simplify the board layout?
The main reason was the "inhibit recovery problem". The inhibit line required a large current that went through all the cores. This caused electrical noise, requiring a delay while the noise settled down. Doing away with the inhibit line thus helped performance. The drive lines are also shorter, which also helps performance.
Funny to see that frontpage as earlier on today I made a comment saying that with LLMs I'm betting we'll see N-modular redundancy systems soon, with a ultra-hardened, minimal, part picking the majority votes of N LLM-written implementations (in different languages, on different stacks, all running at the same time). Not 100% TFA but "computing in space" involved a lot of N-modular redundancy systems.
The reason I'm 99.9% sure we'll see that is that it'll help catch both bugs in the LLMs implementations themselves (and we know there are plenty of those) but also in the stacks/platforms/VMs running those software.
Imagine one spec and five implementations (Rust, Go, Java, Python, whatever) and one minimal system, with the tiniest of the tiniest attack surface, returning the answer as soon as 3-of-5 agree. And, as a bonus, if later on one the two "missing" answer arrives and doesn't match, it's cause for enquiry and bugs be smashed.
Basically (and although I don't care about Ethereum or cryptocurrencies except for the cryptographic aspect), we already witnessed that: 3 different implementations of Ethereum and, in the early days, one of the implementation whose result differed from the two others. And hence the implementation not respecting the spec (in that case it was the only one that was faulty) got instantly detected (and promptly patched). My memory is fuzzy but I know this happened.
Heck, I may write a proof-of-concept for fun.
I've got other ideas as to what will be possible in the future but I'm keeping them for another day.
This all rests on the assumption that design errors are independent beween LLM-generated programs for the same specification. That's not true for humans (Knight and Leveson, 1986) and I highly doubt it's any more true for robots.
(On the other hand I just found out about Ron, Baudry, Monperrus, 2026, which seems to say "sure, problems are correlated, but it could still be useful.")
Author here for all your core memory questions...
No special provisions for rad hardening needed?
Core memory is very resistant to radiation. When the Shuttle computers were upgraded to semiconductor memory, radiation became an issue. The solution was to add six extra bits of storage to each word and use ECC. A background process scanned for errors and corrected them. The computer could encounter 100 bit flips per flight, so radiation was significant. (There was even an incident where a single cosmic ray flipped 14 bits.) The other problem with semiconductor memory was its volatility, so the computer had NiCd batteries for backup power to the RAM.
For details on how radiation affected the Space Shuttle's computers, see this paper: https://klabs.org/DEI/Processor/shuttle/oneill_94.pdf
On the topic of ferromagnetic computing, was there ever any serious investigation of Parametron type machines for at least parts of the flight control or other critical systems where interruptions would have been very serious?
I assume you're interested in magnetic core logic computers in general, not specifically Parametrons. In the late 1950s, NASA considered core-transistor logic for a spacecraft navigation computer due to its lower power consumption. The prototype version of the Apollo Guidance Computer (1962) used core-transistor logic. But improvements in transistors made core-transistor logic less appealing, not to mention the arrival of ICs. At the end of 1962, NASA decided to use ICs for the Apollo Guidance Computer and abandoned core-transistor logic. The updated AGC kept the core memory and core rope ROM of the earlier AGC, though.
Yes, those engineering discussions must have been interesting. By that point people had a fair amount of experience in Earth orbit but between the relative newness of space and the relative newness of computers there must have been significant new engineering. Maybe the ICBM programs had some lessons.
Please write an article about that French computer Project idea: find 64kb kb of such memory and connect it somehow into Apple2, atari and other 8bit cpus hehe
It must be possible to have some hardware adapter to map RAM into that type of memory.
Or even over serial...
ps. Related story: around 10 years ago Texas Instruments started to use FRAM in some of their 16 bit MCUs (msp430 family)
It works exactly like core memory - data still intact after power resets.
I've already written articles about the French computer and FRAM; enjoy :-) https://www.righto.com/2026/05/reverse-engineering-spacelab-... https://www.righto.com/2024/09/ramtron-ferroelectric-fram-di...
FRAM is a somewhat common retrofit for battery-backed SRAM: https://bastelblog.runlevel3.de/en/restore/ds1250-fram-repla...
Amazing how reliable core memory was for critical systems, even in space. Bet it weighed a ton compared to modern RAM.
The architecture without inhibit lines is interesting. Did this make the memory faster, or was the main goal simply to reduce the number of sense amplifiers and simplify the board layout?
The main reason was the "inhibit recovery problem". The inhibit line required a large current that went through all the cores. This caused electrical noise, requiring a delay while the noise settled down. Doing away with the inhibit line thus helped performance. The drive lines are also shorter, which also helps performance.
The paper "2 1/2 D High Speed Memory Systems: Past, Present, and Future" explains this, but not entirely clearly: https://ieeexplore.ieee.org/document/4038821
I saw this in person and then again on Dr Stone
Built by highly skilled humans.
Funny to see that frontpage as earlier on today I made a comment saying that with LLMs I'm betting we'll see N-modular redundancy systems soon, with a ultra-hardened, minimal, part picking the majority votes of N LLM-written implementations (in different languages, on different stacks, all running at the same time). Not 100% TFA but "computing in space" involved a lot of N-modular redundancy systems.
The reason I'm 99.9% sure we'll see that is that it'll help catch both bugs in the LLMs implementations themselves (and we know there are plenty of those) but also in the stacks/platforms/VMs running those software.
Imagine one spec and five implementations (Rust, Go, Java, Python, whatever) and one minimal system, with the tiniest of the tiniest attack surface, returning the answer as soon as 3-of-5 agree. And, as a bonus, if later on one the two "missing" answer arrives and doesn't match, it's cause for enquiry and bugs be smashed.
Basically (and although I don't care about Ethereum or cryptocurrencies except for the cryptographic aspect), we already witnessed that: 3 different implementations of Ethereum and, in the early days, one of the implementation whose result differed from the two others. And hence the implementation not respecting the spec (in that case it was the only one that was faulty) got instantly detected (and promptly patched). My memory is fuzzy but I know this happened.
Heck, I may write a proof-of-concept for fun.
I've got other ideas as to what will be possible in the future but I'm keeping them for another day.
This all rests on the assumption that design errors are independent beween LLM-generated programs for the same specification. That's not true for humans (Knight and Leveson, 1986) and I highly doubt it's any more true for robots.
(On the other hand I just found out about Ron, Baudry, Monperrus, 2026, which seems to say "sure, problems are correlated, but it could still be useful.")