I thought the same when I saw that the financial industry was hiring FPGA people for low-latency algorithms.
My understanding (as a non-FPGA expert) is that currently FPGA beats generic hardware (CPU,GPU) for "small size algorithm" (i.e that do not need GB of weights), while enabling a certain flexibility vs ASIC.
My guess is that you cannot bake all the weights into the circuit topology, so you are still bound by the memory transfer speed (to be double checked).
You could build small ML model like talos-v2. But larger model/LLM requires much more engineering cost than you expected. Optimizing HDL has too many control knob/param to solve by RL.
Tang nano FPGAs are around $10, the idea being to couple with a $25 ARM or RISC-V dev board and offload the math from a streaming store. Coupling this with an older 8GB VRAM board can theoretically run a model whose weights do not fit. The weights get repeatedly run through the MCU/FPGA and the VRAM is used for KV Cache and context. If you connected several via USB and streamed a MoE model expert per FPGA, you could achieve parallelism. Won't be fast, but, many requests could be processed in parallel, as each request shares the large static weights.
The reason for this is, model weights do not need to be randomly accessed. So why store them in expensive RAM.
Cerebras and Qrok seem to be using a very different approach than NVIDIA to get orders of magnitudes speed ups. I'm trying to explore other alternative approaches.
I am doing the initial work on many core dual CPUs. I already have systems with large system RAM and older GPUs with less VRAM, and large SAS HDs, fast SSDs running large open weight LLMs that do not really fit any GPU I own (they offload and/or run on CPU and system RAM, but slowly).
I have the MCUs and FPGAs (in a drawer) and I am retired, and this is my idea of fun.
I am trying to generalize an approach to use large MoE models (with possibly small quants) to run many agents in parallel without spending more on more or bigger GPUs.
I am also doing some edge ML (bird species recognition near the camera) using NPUs (in design phase, yet untested). I have an electronics lab, and I've emulated soft CPUs and built software that runs on FPGAs and in my emulators.
Instead of assuming my approach won't work or is too expensive, I choose to be optimistic. Also, failures are educational. I'm trying to gain more FPGA experience.
No one because FPGAs are 10-20x less dense than ASICs actually designed for purpose. The tooling is also complete shit. Signed someone that did (part of) their PhD on this topic.
I thought the same when I saw that the financial industry was hiring FPGA people for low-latency algorithms.
My understanding (as a non-FPGA expert) is that currently FPGA beats generic hardware (CPU,GPU) for "small size algorithm" (i.e that do not need GB of weights), while enabling a certain flexibility vs ASIC.
My guess is that you cannot bake all the weights into the circuit topology, so you are still bound by the memory transfer speed (to be double checked).
You could build small ML model like talos-v2. But larger model/LLM requires much more engineering cost than you expected. Optimizing HDL has too many control knob/param to solve by RL.
FPGAs are far more expensive than GPU+DRAM, even at today's inflated prices.
Tang nano FPGAs are around $10, the idea being to couple with a $25 ARM or RISC-V dev board and offload the math from a streaming store. Coupling this with an older 8GB VRAM board can theoretically run a model whose weights do not fit. The weights get repeatedly run through the MCU/FPGA and the VRAM is used for KV Cache and context. If you connected several via USB and streamed a MoE model expert per FPGA, you could achieve parallelism. Won't be fast, but, many requests could be processed in parallel, as each request shares the large static weights.
The reason for this is, model weights do not need to be randomly accessed. So why store them in expensive RAM.
Cerebras and Qrok seem to be using a very different approach than NVIDIA to get orders of magnitudes speed ups. I'm trying to explore other alternative approaches.
I predict that the FPGA adds no value in this scenario. Just process inference on the CPU.
I am doing the initial work on many core dual CPUs. I already have systems with large system RAM and older GPUs with less VRAM, and large SAS HDs, fast SSDs running large open weight LLMs that do not really fit any GPU I own (they offload and/or run on CPU and system RAM, but slowly).
I have the MCUs and FPGAs (in a drawer) and I am retired, and this is my idea of fun.
I am trying to generalize an approach to use large MoE models (with possibly small quants) to run many agents in parallel without spending more on more or bigger GPUs.
I am also doing some edge ML (bird species recognition near the camera) using NPUs (in design phase, yet untested). I have an electronics lab, and I've emulated soft CPUs and built software that runs on FPGAs and in my emulators.
Instead of assuming my approach won't work or is too expensive, I choose to be optimistic. Also, failures are educational. I'm trying to gain more FPGA experience.
Train circuits, not weights; then use an FPGA
Can you suggest what circuits? examples?
No one because FPGAs are 10-20x less dense than ASICs actually designed for purpose. The tooling is also complete shit. Signed someone that did (part of) their PhD on this topic.
But I can afford my already purchased drawer full of cheap FPGAs for experiments.
I guess I am too risk adverse to bet $10,000 on an ASIC run (having no experience doing that and no desire to go that route).
If I can demonstrate a proof-of-concept in a reproducible research way, others can then advance to the ASIC level.
This is just a hobbyist experiment looking for other hobbyists who can afford a cheap FPGA and have some free time and interest.